Hello, I'm

Karthikeya Mandava

MS ECE @ Rutgers · SoC DV Engineer

Get To Know More

About Me

Industry Experience

4+ years
SoC Design Verification
Intel · Renesas

Education

MS ECE — Rutgers (4.0 GPA)
BTech ECE — First Class

Research

Thesis: Cache-Coherent
Attestation Controller
(CAC)

I'm an MS ECE student at Rutgers University (GPA 4.0) specialising in secure and energy-efficient hardware design. My thesis work focuses on the Cache-Coherent Attestation Controller (CAC) — a hardware architecture for runtime memory integrity in cache-coherent SoCs, prototyped on Xilinx Zynq UltraScale+ with PicoRV32 RISC-V cores. Before Rutgers, I spent 4+ years as a Design Verification engineer at Sankalp Semiconductor (HCLTech) and Qsocs Technologies, working on SoC projects for Intel and Renesas. I specialise in UVM-based verification, low-power design (UPF), cache coherence protocols, and hardware security.

Where I've Worked

Experience

Sankalp Semiconductor (HCLTech)

Member Technical Staff — Design Verification

Nov 2021 – Jul 2024 · Bangalore, India

Led pre-Si low-power verification (UPF / DVS / clock gating) — 12% SoC efficiency gain
RTL verification of 15+ IPs at 95% coverage (clients: Renesas UWB SoC, Intel NVMe-oF)
Mentored 5 engineers; reduced bug resolution turnaround by 20%

Qsocs Technologies

Jr. Verification Engineer

Oct 2019 – Sep 2021 · Bangalore, India

VIP development for AHB / AXI protocols — 97% functional coverage
Regression automation improved verification efficiency by 15%
Resolved 20+ critical protocol violations in interconnect fabric

What I Work With

Skills

HDL & Languages

SystemVerilog / Verilog

Experienced

VHDL

Intermediate

C / C++

Intermediate

Python / Shell / TCL

Experienced

SystemC

Intermediate

Verification & Tools

UVM

Experienced

Formal (SVA / JasperGold)

Intermediate

Questa / VCS / Verdi

Experienced

Low-Power (UPF)

Experienced

gem5 / QEMU

Intermediate

Vivado / FPGA

Intermediate

Protocols & Domains

AMBA (AXI4 / AHB / APB)

Experienced

PCIe / NVMe-oF

Intermediate

Cache Coherence (MESIF)

Experienced

Hardware Security / TPM

Intermediate

UART / SPI / I2C

Experienced

MS Research

Thesis

Cache-Coherent Attestation Controller (CAC)

Hardware Architecture for Runtime Memory Integrity in Cache-Coherent SoCs

Jan 2025 – May 2026 · Rutgers University

Modern hardware attestation systems operate at the DRAM level, leaving a critical blind spot: in-flight cache lines that may hold compromised data not yet written back to memory. CAC closes this gap by integrating attestation directly into the cache coherence protocol, enabling deterministic memory integrity snapshots even under adversarial write pressure.

100%

Detection rate vs 20–40% false negative in DRAM-only baselines

MESIF

Custom coherence protocol with directory-level freeze mechanism

ZCU102

Xilinx Zynq UltraScale+ · PicoRV32 RISC-V · AXI4 · SHA-3

SystemVerilog FPGA (Vivado) PicoRV32 RISC-V AXI4 SHA-3 Python Cache Coherence Hardware Security

Browse My

Projects

Cache & Architecture

Academic

MESIF Cache Coherency & Performance Optimization

Sep 2024 – Dec 2024

SystemVerilog EDA Playground Xcelium

RTL implementation of a 4-core MESIF cache coherence protocol with directory controller and state machine. Benchmarked performance across core configurations with waveform-level validation.

Academic

SIMD Matrix Multiply Across x86 / ARM / RISC-V

Sep 2024 – Dec 2024

C SIMD / AVX2 gem5 QEMU

4.5× speedup on x86 AVX2; 3.2× on ARM NEON; simulated on RISC-V via gem5. 18% L2 cache miss reduction. Benchmarked IPC and energy efficiency across matrix sizes and ISA implementations.

Research

NUMA Sensitivity Across Computational Kernels

Sep 2025 – Dec 2025 · Princeton University

C Python STREAM perf MPI

Characterised NUMA placement impact across microbenchmarks (STREAM Triad, pointer-chasing) and application kernels on dual-socket Intel Xeon. Group research project at Princeton (ECE 580).

Hardware Security

Academic

Flush+Reload Side-Channel Mitigation in MESIF CMPs

Jan 2025 – May 2025

SystemVerilog Python ModelSim

Hardware-assisted mitigation of Flush+Reload cache side-channels in MESIF chip-multiprocessors. Timing obfuscation and traffic shaping achieved 28% correlation reduction and 12% bus traffic improvement.

Academic

Secure Boot & Rollback Protection via TPM 2.0

Jan 2025 – May 2025

Python TPM 2.0 swtpm RSA-2048 Bash

Software-based secure boot using a TPM 2.0 simulator — no physical hardware required. Validates firmware integrity via PCR measurement and RSA key hierarchy. Tested rollback attack detection latency.

Academic

Secure Boot on Zybo Z7 FPGA

Jan 2025 – May 2025

FPGA Vivado C UART

End-to-end secure boot on Zybo Z7-7000. Validates firmware authenticity via RSA signature verification before execution — mirroring early-stage secure boot used in production embedded hardware.

HPC Research

Research

Quantifying NUMA-Induced Memory Heterogeneity in HPC

Fall 2025 · Term Paper

Python perf Intel Xeon NUMA

Quantified NUMA latency and bandwidth asymmetry on a dual-socket Intel Xeon Platinum 8352Y (Ice Lake). Studied impact of suboptimal memory placement and thread binding on HPC workload performance.

Research

Adaptive Workflow Systems for HPC: A Gap Analysis

Fall 2025 · Midterm Paper

HPC Scheduling Survey

Identified fundamental gaps in adaptive scientific workflow systems — specifically batch scheduler limitations for iterative ML-driven workloads like molecular dynamics simulations.

Industry Work

Industry

UWB SoC Verification (Renesas)

Jan 2023 – Jul 2024

SystemVerilog UPF Python

Full functional coverage on RIIC, ADC, RLIN, WDTB modules. UPF-based low-power verification with optimised power state transitions.

🔒 Industry project — NDA

Industry

NVMe-oF IP Verification (Intel)

Nov 2021 – Dec 2022

SystemVerilog UVM Python

95%+ coverage on RDMA command validation. Python regression automation reduced runtime by 20%. Resolved critical timing bugs and protocol violations.

🔒 Industry project — NDA

Industry

VIP Dev & AHB Interconnect (Qsocs)

Oct 2019 – Sep 2021

UVM SystemVerilog Questasim

Reusable VIPs for AMBA protocols (AXI, AHB, UART, SPI, I2C). Multi-master AHB interconnect verification achieving AXI 4.0 compliance.

🔒 Industry project — NDA

Get in Touch

Contact Me

karthikeya.mandava@rutgers.edu